Fort George G Meade, MD

FPGA/ASIC Design Engineer – TS/SCI w/ FS Poly Clearance Required

Job Title:

FPGA/ASIC Design Engineer with Top Secret/SCI Full Scope Polygraph Clearance Required


Fort George G Meade, MD

About Us:

Our Client is a locally owned small business that specializes in delivering high-end engineering products and services to our customers. Our employees have a wide variety of engineering skills and talents in hardware, software and system engineering to solve the most challenging technical problems facing our customers. Our employees are detail-oriented, customer-focused, and enjoy working in a dynamic and productive team environment.

About the Job:

Our Client is looking for a customer-focused team player working on-site in a mission-oriented environment. The candidate must be a self-starter, possess good communication skills, and be willing to interface with multiple teams throughout the design process.

We are currently seeking FPGA design engineers with emphasis on FPGA or ASIC design, development and verification using SystemVerilog, Verilog or VHDL. The design engineer will work closely with software and system engineers to conceptualize, document, design, code, verify and lab-debug ASIC, FPGA and embedded firmware designs. The ideal candidate will be adaptable, motivated, customer oriented, able to lead a small team and willing to mentor others while learning new technologies.


  • Must currently possess an active TS/SCI Clearance with Full-Scope Polygraph (FSP).
  • Experience using VHDL RTL Coding (for design and/or analysis of digital circuits)
  • Experience with FPGA Design, synthesis, P&R tools (ex Vivado, Quartus)
  • Experience utilizing Verilog/System and Verilog test bench development
  • Experience working with Linux/Windows OS
  • Knowledge of design simulation tools (Mentor, Cadence, Synopsys - 1 or more)
  • Strong oral/written communication
  • Location is onsite at Fort Meade, MD.

You Could Also Have This

  • Experience with Verilog RTL Coding
  • Experience with ASIC/FPGA front-end design and architecture of cryptographic systems
  • Experience using soft/hard IP cores in FPGAs/ASICs (ex Zynq or Microblaze or RISC processors, memories, flash/NVM)
  • Experience in Reverse Engineering of digital designs from one or more levels of abstraction (ex from images of deprocessed hardware, GDS2 data, netlists, etc.)
  • Knowledge of ASIC implementation methods/tools (synthesis, physical layout - Cadence/Synopsys)
  • Knowledge of formal verification tools
  • Knowledge of semiconductor manufacturing processes
  • Strong C/C++, Python, Perl or scripting


Multiple openings for Junior, Senior, Principal and Sr. Principal Engineers: Minimum three (3) years’ experience as a Design Engineer in integrated circuit or microelectronic component design or reverse engineering of the same is required. Bachelor’s degree in Electrical Engineering or Computer Engineering from an accredited college or university is required. Five (5) years of additional hardware design engineering experience may be substituted for a bachelor’s degree.

Our Client offers a great work environment/culture with excellent compensation and benefits for our employees. Our benefits include employer paid medical, dental and vision insurance, 25 days of paid time off, 10 government holidays, excellent 401K (6% employer contribution and 9% profit sharing), and flexible work schedule and comp time policy.

Our Client is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or protected

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